Symbolic Extraction for Estimating Analog Layout Parasitics in Layout-Aware Synthesis

Tseng, I., Postula, A. J. and Jozwiak, L. (2005). Symbolic Extraction for Estimating Analog Layout Parasitics in Layout-Aware Synthesis. In: Andrzej Napieralski, Proceedings of the 12th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2005). The 12th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES'05), Krakow, Poland, (195-199). 22-25 June, 2005.

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Author Tseng, I.
Postula, A. J.
Jozwiak, L.
Title of paper Symbolic Extraction for Estimating Analog Layout Parasitics in Layout-Aware Synthesis
Conference name The 12th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES'05)
Conference location Krakow, Poland
Conference dates 22-25 June, 2005
Proceedings title Proceedings of the 12th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES 2005)
Place of Publication Krakow, Poland
Publisher Department of Microelectronics and Computer Science, Technical University of Lodz, Poland
Publication Year 2005
Sub-type Fully published paper
ISBN 83-919289-9-3
Editor Andrzej Napieralski
Volume 1
Start page 195
End page 199
Total pages 5
Collection year 2005
Language eng
Abstract/Summary This paper presents a new layout parasitics extraction paradigm, symbolic extraction, for use in layout-aware analog synthesis methodologies. Unlike traditional post-layout extraction, symbolic extraction extracts layout parasitics in symbolic form from parameterized layouts. As a result, parasitic values can be calculated directly from given circuit and layout parameters. In layout-aware circuit synthesis process, tasks of time-consuming layout re-gerenarion and re-extraction can be replaced by this fast parasitics calculation step. In the paper, we discuss how to integrate symbolic extraction into the existing analog design flow and how symbolic extraction can be implemented.
Subjects 290903 Other Electronic Engineering
290901 Electrical Engineering
290902 Integrated Circuits
290900 Electrical and Electronic Engineering
E1
700199 Computer software and services not elsewhere classified
Keyword symbolic extraction
analog design methodology
layout parasitics extraction
physical design
parameterized layout
Q-Index Code E1

 
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Created: Fri, 19 Aug 2005, 10:00:00 EST by I-lun Tseng on behalf of School of Information Technol and Elec Engineering