The value of a small microkernel for dreamy memory and the RAMpage memory hierarchy

Machanick, Philip (2005) The value of a small microkernel for dreamy memory and the RAMpage memory hierarchy. Journal of Computer Science and Technology, 20 5: 586-595. doi:10.1007/s11390-005-0586-z

Author Machanick, Philip
Title The value of a small microkernel for dreamy memory and the RAMpage memory hierarchy
Journal name Journal of Computer Science and Technology   Check publisher's open access policy
ISSN 1000-9000
Publication date 2005-09-01
Sub-type Article (original research)
DOI 10.1007/s11390-005-0586-z
Volume 20
Issue 5
Start page 586
End page 595
Total pages 10
Editor Guo-Jie Li
Place of publication New York, United States
Publisher Springer
Language eng
Subject C1
291602 Memory Structures
671299 Computer hardware and electronic equipment not elsewhere classified
Abstract This paper explores potential for the RAMpage memory hierarchy to use a microkernel with a small memory footprint, in a specialized cache-speed static RAM (tightly-coupled memory, TCM). Dreamy memory is DRAM kept in low-power mode, unless referenced. Simulations show that a small microkernel suits RAMpage well, in that it achieves significantly better speed and energy gains than a standard hierarchy from adding TCM. RAMpage, in its best 128KB L2 case, gained 11% speed using TCM, and reduced energy 14%. Equivalent conventional hierarchy gains were under 1%. While 1MB L2 was significantly faster against lower-energy cases for the smaller L2, the larger SRAM's energy does not justify the speed gain. Using a 128KB L2 cache in a conventional architecture resulted in a best-case overall run time of 2.58s, compared with the best dreamy mode run time (RAMpage without context switches on misses) of 3.34s, a speed penalty of 29%. Energy in the fastest 128KB L2 case was 2.18J vs. 1.50J, a reduction of 31%. The same RAMpage configuration without dreamy mode took 2.83s as simulated, and used 2.39J, an acceptable trade-off (penalty under 10%) for being able to switch easily to a lower-energy mode.
Keyword Computer Science, Hardware & Architecture
Computer Science, Software Engineering
Low-power Design
Main Memory
Virtual Memory
Cache Memories
Q-Index Code C1

Document type: Journal Article
Sub-type: Article (original research)
Collections: 2006 Higher Education Research Data Collection
School of Information Technology and Electrical Engineering Publications
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Created: Wed, 15 Aug 2007, 17:15:38 EST