FPGA implementations of ladder diagrams

Bergmann, Neil William, Waldeck, Peter and Shukla, Sunil K. (2013) FPGA implementations of ladder diagrams. Modern Applied Science, 7 3: 64-73. doi:10.5539/mas.v7n3p64

Author Bergmann, Neil William
Waldeck, Peter
Shukla, Sunil K.
Title FPGA implementations of ladder diagrams
Journal name Modern Applied Science   Check publisher's open access policy
ISSN 1913-1844
Publication date 2013-02-26
Sub-type Article (original research)
DOI 10.5539/mas.v7n3p64
Open Access Status DOI
Volume 7
Issue 3
Start page 64
End page 73
Total pages 10
Place of publication Toronto, ON, Canada
Publisher Canadian Center of Science and Education
Language eng
Abstract Sequential control is an elementary technology for manufacturing systems. Many manufacturing devices or systems are usually controlled by Programmable Controllers (PCs). In order to satisfy the requirements of downsizing and information hidden, we develop a new type controller, which is implemented using Field Programmable Gate Array (FPGA) as an Application Specific Integrated Circuit (ASIC). The widely used programming language in the area of sequential control, Ladder Diagram (LD), is also implemented on such FPGA. The main bottleneck of the implementation is how to realize cyclic scan, which is the most significant characteristic of PCs. In this paper, we describe two methods to implement the cyclic scan. One is of using the clock event of the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), and the other is of translating coil as a self-hold circuit of LD into an appropriate flip-flop element of VHDL. We also compare the two methods and show the benefits of the new controller implemented by FPGA.
Q-Index Code C1
Q-Index Status Confirmed Code
Institutional Status UQ

Document type: Journal Article
Sub-type: Article (original research)
Collections: Official 2014 Collection
School of Information Technology and Electrical Engineering Publications
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Created: Sun, 03 Mar 2013, 01:24:30 EST by Professor Neil Bergmann on behalf of School of Information Technol and Elec Engineering