An ILP formulation for architectural syntesis and application mapping on FPGA-Based hybrid multi-processor SoC

Wu, J., Williams, J.A. and Bergmann, N.W. (2008). An ILP formulation for architectural syntesis and application mapping on FPGA-Based hybrid multi-processor SoC. In: Kebschull, U., Platzner, M. and Teich, J., Proceedings, 2008 International Conference on Field-Programmable Logic and Applications. 2008 International Conference on Field Programmable Logic and Applications (FPL), Heidelberg, Germany, (451-454). 8-10 September, 2008. doi:10.1109/FPL.2008.4629981

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Author Wu, J.
Williams, J.A.
Bergmann, N.W.
Title of paper An ILP formulation for architectural syntesis and application mapping on FPGA-Based hybrid multi-processor SoC
Conference name 2008 International Conference on Field Programmable Logic and Applications (FPL)
Conference location Heidelberg, Germany
Conference dates 8-10 September, 2008
Proceedings title Proceedings, 2008 International Conference on Field-Programmable Logic and Applications
Journal name Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL
Place of Publication Heidelberg Germany
Publisher IEEE
Publication Year 2008
Sub-type Fully published paper
DOI 10.1109/FPL.2008.4629981
Open Access Status
ISBN 978-1-4244-1961-6
Editor Kebschull, U.
Platzner, M.
Teich, J.
Start page 451
End page 454
Total pages 4
Language eng
Subjects E1
100606 Processor Architectures
890202 Application Tools and System Utilities
Keyword ILP formulation
architectural syntesis
application mapping
FPGA
multi-processor
SoC
Q-Index Code E1
Q-Index Status Confirmed Code

 
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Created: Sun, 05 Apr 2009, 19:25:20 EST by Donna Clark on behalf of School of Information Technol and Elec Engineering