System level design methodology for Hybrid Multi-Processor SoC on FPGA

Wu, J., Williams, J. and Bergmann, N.W. (2008). System level design methodology for Hybrid Multi-Processor SoC on FPGA. In: Poek, K.L. and Buell, D., Proceedings of the Sixteenth IEEE Symposium on Field-Programmable Custom Computing Machines. The Sixteenth IEEE Symposium on Field-Programmable Custom Computing Machines, Stanford, USA, (312-313). 14-15 April, 2008. doi:10.1109/FCCM.2008.45


Author Wu, J.
Williams, J.
Bergmann, N.W.
Title of paper System level design methodology for Hybrid Multi-Processor SoC on FPGA
Conference name The Sixteenth IEEE Symposium on Field-Programmable Custom Computing Machines
Conference location Stanford, USA
Conference dates 14-15 April, 2008
Convener IEEE Computer Society
Proceedings title Proceedings of the Sixteenth IEEE Symposium on Field-Programmable Custom Computing Machines
Journal name Proceedings of the Sixteenth Ieee Symposium On Field-Programmable Custom Computing Machines
Place of Publication Los Alamatis, California
Publisher IEEE
Publication Year 2008
Sub-type Fully published paper
DOI 10.1109/FCCM.2008.45
Open Access Status
ISBN 978-0-7695-3307-0
Editor Poek, K.L.
Buell, D.
Start page 312
End page 313
Total pages 2
Language eng
Abstract/Summary In this paper, we present a reconfigurable system on chip design framework that generates an architectural design along with binding and scheduling algorithm, specific to the input application in Kahn Process Network specification.The likelihood that tasks and communication channels may have many potential physical manifestations is explicitly recognised and embraced, to assist the design exploration process. The architectural design, binding and scheduling problems are formulated as a Integer Linear Programming problem, with physical constraints such as available logic resources, computation time and memory footprints to guide the design space exploration.
Subjects E1
100606 Processor Architectures
890202 Application Tools and System Utilities
Keyword FPGA
Hybrid multi-processor
SoC
Mapping
Scheduling
System-Level Design
Q-Index Code E1
Q-Index Status Confirmed Code

Document type: Conference Paper
Sub-type: Fully published paper
Collections: 2009 Higher Education Research Data Collection
School of Information Technology and Electrical Engineering Publications
 
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Created: Sun, 05 Apr 2009, 19:18:58 EST by Donna Clark on behalf of School of Information Technol and Elec Engineering