Code compression based on operand-factorization for VLIW processors

Ros, M. B. and Sutton, P. R. (2004). Code compression based on operand-factorization for VLIW processors. In: J. Storer and M. Cohn, Proceedings of the Data Compression Conference 2004 (DCC 2004). The Data Compression Conference 2004 (DCC 2004), Snowbird, Utah, U.S.A., (559-559). 23-25 March 2004. doi:10.1109/DCC.2004.1281535

Author Ros, M. B.
Sutton, P. R.
Title of paper Code compression based on operand-factorization for VLIW processors
Conference name The Data Compression Conference 2004 (DCC 2004)
Conference location Snowbird, Utah, U.S.A.
Conference dates 23-25 March 2004
Proceedings title Proceedings of the Data Compression Conference 2004 (DCC 2004)
Journal name Dcc 2004: Data Compression Conference, Proceedings
Series Data Compression Conference Proceedings
Place of Publication Los Alamitos, California, U.S.A.
Publisher IEEE Computer Society
Publication Year 2004
Sub-type Fully published paper
DOI 10.1109/DCC.2004.1281535
Open Access Status Not yet assessed
ISBN 0-7695-2082-0
ISSN 1068-0314
Editor J. Storer
M. Cohn
Start page 559
End page 559
Total pages 1
Language eng
Abstract/Summary As programs become more complex for both embedded systems and large-scale applications, bloated code size continues to be an ever increasing problem. The size of object code greatly effects the space used and ultimately contributes greatly to cost. Code compression techniques have been devised as a way of battling large code. Code compression algorithms usually require specific techniques to maintain the integrity of the program and ensure its functionality. This paper presents three code compression algorithms based on dictionary methods for entire instructions, instructions factorized into op-code/operand pairs and operand factorization applied to instruction words. MediaBench benchmarks are compiled for maximum code optimization on the TI TMS320C6x then compressed. Compression Ratios (defined as the ratio of compressed code to uncompressed code) of 81.5%, 68.3% and 84.7% are reported for the three compression schemes. The instruction-based factorization scheme outperforms the other schemes in relation to code size, but requires sequential decompression of unit instructions. Operand factorization across instruction words allows for decompression of instructions in parallel at a cost to the compression ratio.
Subjects EX
291605 Processor Architectures
671201 Integrated circuits and devices
Q-Index Code EX
Institutional Status UQ

Version Filter Type
Citation counts: TR Web of Science Citation Count  Cited 4 times in Thomson Reuters Web of Science Article | Citations
Scopus Citation Count Cited 12 times in Scopus Article | Citations
Google Scholar Search Google Scholar
Created: Fri, 24 Aug 2007, 05:36:58 EST