A Layout-Aware Circuit Sizing Model Using Parametric Analysis

Tseng, I-Lun and Postula, Adam (2004). A Layout-Aware Circuit Sizing Model Using Parametric Analysis. In: Y. Takeuchi, Proceedings of the Workshop on Synthesis and System Integration of Mixed Information Technologies. The 12th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI'04), Kanazawa, Japan, (235-240). 18-19 October, 2004.

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Author Tseng, I-Lun
Postula, Adam
Title of paper A Layout-Aware Circuit Sizing Model Using Parametric Analysis
Conference name The 12th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI'04)
Conference location Kanazawa, Japan
Conference dates 18-19 October, 2004
Proceedings title Proceedings of the Workshop on Synthesis and System Integration of Mixed Information Technologies
Place of Publication Hiroshima, Japan
Publisher SASIMI Workshop
Publication Year 2004
Sub-type Fully published paper
Editor Y. Takeuchi
Volume 1
Start page 235
End page 240
Total pages 6
Collection year 2004
Language eng
Abstract/Summary We propose a circuit sizing model that takes layout parasitics into account. The circuit and layout parameters are stored in a parameterized layout description format, GBLD. The layout parasitics are stored as closed form expressions. Layout optimization tools can modify the layout and recalculate parasitics on the fly. If the results of sensitivity analysis are passed to those tools, optimization for performance can be achieved with relatively few iterations involving time consuming circuit simulations.
Subjects 290903 Other Electronic Engineering
290901 Electrical Engineering
290902 Integrated Circuits
290900 Electrical and Electronic Engineering
E1
700199 Computer software and services not elsewhere classified
Keyword circuit sizing
models
layout parameters
optimisation
performance
Q-Index Code E1

 
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Created: Mon, 21 Feb 2005, 10:00:00 EST by I-lun Tseng on behalf of School of Information Technol and Elec Engineering