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Accurate Modeling of the Effects of Fringing Area Interface Traps on Scanning Capacitance Microscopy Measurement
Hong, Yang David, Yeow, YewTong, Chim, Wai Kin, Yan, Jian and Wong, Kin Mun (2006) Accurate Modeling of the Effects of Fringing Area Interface Traps on Scanning Capacitance Microscopy Measurement. IEEE Transactions on Electron Devices, 53 3: 499-506.
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published_paper.pdf
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published_paper.pdf
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application/pdf
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477.24KB
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164
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| Author
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Hong, Yang David
Yeow, YewTong
Chim, Wai Kin
Yan, Jian
Wong, Kin Mun
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| Title
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Accurate Modeling of the Effects of Fringing Area Interface Traps on Scanning Capacitance Microscopy Measurement
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| Journal name
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IEEE Transactions on Electron Devices (ERA 2012 Listed) (ERA 2010 Rank A) Check publisher's open access policy
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| Publication date
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2006-03-01
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| Sub-type
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Article
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| DOI
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10.1109/TED.2005.864367
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| Volume number
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53
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| Issue number
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3
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| ISSN
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0018-9383
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| Start page
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499
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| End page
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506
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| Total pages
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8
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| Editor
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D. P. Verret
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| Place of publication
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New York
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| Publisher
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IEEE-Inst Electrical Electronics Engineers Inc
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| Language
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eng
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| Subject
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290901 Electrical Engineering
290900 Electrical and Electronic Engineering
290902 Integrated Circuits
671201 Integrated circuits and devices
C1
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| Abstract
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Scanning capacitance microscopy (SCM) is a dopant profile extraction tool with nanometre spatial resolution. While it is based on the high-frequency MOS capacitor theory, there are crucial second-order effects which make the extraction of dopant profile from SCM data a challenging task. Due to small size of the SCM probe, the trapped charges in the interface traps at the oxide-silicon dioxide interface surrounding the probe significantly affect the measured SCM data through the fringing electric field created by the trapped charges. In this paper, we present numerical simulation results to investigate the nature of SCM dC/dV data in the presence of interface traps. The simulation takes into consideration the traps response to the ac signal used to measure dC/dV as well as the fringing field of the trapped charge surrounding the probe tip. In the study, we present an error estimation of experimental SCM dopant concentration extraction when the interface traps and fringing field are ignored. The trap distribution in a typical SCM sample is also investigated.
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| Keyword
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scanning capacitance microscopy
dopant profile extraction
semiconductor device modeling
simulation
interface traps
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| References
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1.The International Technology Roadmap for Semiconductors, 2003 Edition, Metrology, Semiconductor Industry Association, San Jose, CA: 2003, pp. 38. 2.A.C. Diebold, M.R. Kump, J.J. Kopanski and D.G. Seiler, "Characterization of two-dimensional dopant profiles: status and review," J. Vac. Sci. Technol. B 14, pp.196-201, 1996. 3.C. C. Williams, "Two-dimensional dopant profiling by scanning capacitance microscopy," Annu. Rev. Mater. Sci. pp. 471-504, 1999. 4.E.H. Nicollian and J. R. Brews, MOS Physics and Technology, Chap. 8, Wiley, New York, 1982. 5.Y. Huang, C. C. Williams, "Capacitance-voltage measurement and modelling on a nanometer scale by scanning C-V microscopy," J. Vac. Sci. Technol. B 12, pp. 369-372, 1994. 6.Y. Huang and C.C. Williams, "Quantitative two-dimensional dopant profile measurement and inverse modelling by scanning capacitance microscopy," Appl. Phys. Lett. 66, pp 344-346, 1995. 7.J. J. Kopanski, J. F. Marchiando and B.G. Rennex, "Carrier concentration dependence of the scanning capacitance microscopy signal in the vicinity of p-n junctions," J. Vac. Sci. Technol. B 18, pp. 409-413, 2000. 8.V. V. Zavyalov, J. S. McMurray, S.D. Stirling and C.C. Williams, "Two dimensional dopant and carrier profiles obtained by scanning capacitance microscopy on an actively biased cross-sectioned metal-oxide-semiconductor field-effect transistor," J. Vac. Sci. Technol. B18, pp. 549-554, 2000 9.J. J. Kopanski, "Scanning Capacitance Microscopy," The Encyclopaedia of Imaging Science and Technology, John Wiley & Sons, New York, 2001. 10.A.G. Grove, E. H. Snow, B. E. Deal and C. T. Sah, "Simple physical model for the space-charge capacitance of metal-oxide-semiconductor structures," J. Appl. Phys. vol 35, pp. 2458-2460, 1964. 11.Y. D. Hong, Y. T. Yeow, W. K. Chim, K. M. Wong and J. J. Kopanski, "Influence of interface traps and surface mobility degradation on scanning capacitance microscopy measurement," IEEE Trans. Electron Devices, Vol. 51. No. 9, pp. 1496-1503, 2004. 12.G. H. Buh, J. J. Kopanski, J. F. Marchiando, and A. G. Birdwell, "Factors influencing the capacitance-voltage characteristics measured by the scanning capacitance microscope," J. Appl. Phys. vol 94, pp. 2680-2685, 2003. 13.E. H. Poindexter, "MOS interface states: overview and physicochemical perspective," Semicond. Sci. Technol. 4, pp. 961-969, 1989. 14.A. Many, Y. Goldstein and N. B. Grover, Semiconductor Surfaces, Chap. 4, North-Holland, Amsterdam, 1965. 15.J. F. Marchiando, J. J. Kopanski, and J. Albers, "Limitations of the calibration curve method for determining dopant profiles from scanning capacitance microscope measurements," J. Vac. Sci. Technol. B 18, pp. 414-417, 2000. 16.The multiple dopant step wafer piece was purchased from IMEC, 75 Kapeldreef, B-3001 Leuven, Belgium. 17.M. H. White and J. R. Cricchi, "Characterization of thin-oxide MNOS memory transistors," IEEE Trans. Electron Device, Ed-19, No. 12, pp. 1280-1288, 1972.
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| Q-Index Code
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C1
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| Additional Notes
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Citation: Hong, Y. D. and Yeow, Y. T. and Chim, W. K. and Wong, K. M. and Kopanski, J. J. (2004) Influence of Interface Traps and Surface Mobility Degradation on Scanning Capacitance Microscopy Measurement. IEEE Transactions on Electron Devices 51(9):1496-1503. Digital Object Identifyer 10.1109/TED.2005.864367 Copyright (c) YYYY IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
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