Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs

Hsu, C. T., Lau, M. M. and Yeow, Y. T. (2001) Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs. Microelectronics Reliability, 41 2: 201-209. doi:10.1016/S0026-2714(00)00222-5


Author Hsu, C. T.
Lau, M. M.
Yeow, Y. T.
Title Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs
Journal name Microelectronics Reliability   Check publisher's open access policy
ISSN 0026-2714
Publication date 2001-02
Sub-type Article (original research)
DOI 10.1016/S0026-2714(00)00222-5
Volume 41
Issue 2
Start page 201
End page 209
Total pages 9
Editor N. D. Stojadinovic
M. G. Pecht
Place of publication Oxford
Publisher Pergamon
Collection year 2001
Language eng
Subject C1
290902 Integrated Circuits
671201 Integrated circuits and devices
Abstract The use of gate-to-drain capacitance (C-gd) measurement as a tool to characterize hot-carrier-induced charge centers in submicron n- and p-MOSFET's has been reviewed and demonstrated. By analyzing the change in C-gd measured at room and cryogenic temperature before and after high gate-to-drain transverse field (high field) and maximum substrate current (I-bmax) stress, it is concluded that the degradation was found to be mostly due to trapping of majority carriers and generation of interface states. These interface states were found to be acceptor states at top half of band gap for n-MOSFETs and donor states at bottom half of band gap for p-MOSFETs. In general, hot electrons are more likely to be trapped in gate oxide as compared to hot holes while the presence of hot holes generates more interface states. Also, we have demonstrated a new method for extracting the spatial distribution of oxide trapped charge, Q(ot), through gate-to-substrate capacitance (C-gb) measurement. This method is simple to implement and does not require additional information from simulation or detailed knowledge of the device's structure. (C) 2001 Elsevier Science Ltd. All rights reserved.
Keyword Computer Science, Hardware & Architecture
Engineering, Electrical & Electronic
Nanoscience & Nanotechnology
Physics, Applied
Charge
Injection
Channel
Model
Q-Index Code C1

Document type: Journal Article
Sub-type: Article (original research)
Collection: School of Information Technology and Electrical Engineering Publications
 
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Created: Tue, 14 Aug 2007, 16:09:19 EST