Fault tolerant aspects of a dynamic dataflow architecture - PATTSY

Lakshmi Narasimhan V. and Downs T. (1991) Fault tolerant aspects of a dynamic dataflow architecture - PATTSY. Microprocessing and Microprogramming, 32 1-5: 243-252. doi:10.1016/0165-6074(91)90354-V


Author Lakshmi Narasimhan V.
Downs T.
Title Fault tolerant aspects of a dynamic dataflow architecture - PATTSY
Journal name Microprocessing and Microprogramming
ISSN 0165-6074
Publication date 1991
Sub-type Article (original research)
DOI 10.1016/0165-6074(91)90354-V
Volume 32
Issue 1-5
Start page 243
End page 252
Total pages 10
Subject 2200 Engineering
Abstract One of the very significant potential advantages of multiprocessor computing systems is the possibility of graceful degradation in the presence of faults. Prerequisites for fault tolerance in multiprocessor systems are an ability to detect and locate node and link failures, detection and prevention of system deadlocks and, algorithms for distributed checkpointing, rollover and rescheduling of the various program modules. This paper deals with these issues in the context of an alternative multiprocessing system, namely, the dynamic dataflow system. The machine described in this paper employs a localised switching protocol, a special arbiter called the batching arbiter and a new bus structure. Several niovel actors have also been implemented to deal with the various issues of fault tolerance in the system. It is shown in the paper that our machine offers a considerable degree of fault tolerance when compared with most other dataflow systems proposed and/or built.
Keyword Batching arbiter
Dataflow computing
Deadlock elimination and Fault tolerance
Rollover mechanism
Q-Index Code C1
Q-Index Status Provisional Code
Institutional Status Unknown

Document type: Journal Article
Sub-type: Article (original research)
Collection: Scopus Import
 
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Created: Tue, 09 Aug 2016, 04:23:44 EST by System User