FPGA implementation of a high-speed, realtime, windowed standard deviation filter

Herbert, J., Wilson, S., Rakic, A. D. and Taimre, T. (2016) FPGA implementation of a high-speed, realtime, windowed standard deviation filter. Electronics Letters, 52 1: 22-23. doi:10.1049/el.2015.2407


Author Herbert, J.
Wilson, S.
Rakic, A. D.
Taimre, T.
Title FPGA implementation of a high-speed, realtime, windowed standard deviation filter
Journal name Electronics Letters   Check publisher's open access policy
ISSN 0013-5194
1350-911X
Publication date 2016-01-08
Sub-type Article (original research)
DOI 10.1049/el.2015.2407
Open Access Status Not Open Access
Volume 52
Issue 1
Start page 22
End page 23
Total pages 2
Place of publication Stevenage, Herts, United Kingdom
Publisher Institution of Engineering and Technology
Collection year 2017
Language eng
Abstract Characterisation of the standard deviation of a time-series signal has uncommon, yet widespread applications. The usual requirement for a representation of signal standard deviation in real-time implies a high computation speed. A method based on a field programmable gate array (FPGA) implementation is presented. The technique is benchmarked against conventional computational approaches and shows a single windowed standard deviation update calculation of a 16 bit sample can be achieved in 11 ns on a modern CPU. The FPGA implementation is found to be superior to all other approaches examined with an operation time of below 10 ns, and thus provides a useful tool for the real-time measurement of the standard deviation of signals above 100 MHz.
Q-Index Code C1
Q-Index Status Provisional Code
Institutional Status UQ

Document type: Journal Article
Sub-type: Article (original research)
Collections: HERDC Pre-Audit
School of Information Technology and Electrical Engineering Publications
 
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