A hardware scheduler based on task queues for FPGA-based embedded real-time systems

Tang, Yi and Bergmann, Neil W. (2015) A hardware scheduler based on task queues for FPGA-based embedded real-time systems. IEEE Transactions on Computers, 64 5: 1254-1267. doi:10.1109/TC.2014.2315637

Attached Files (Some files may be inaccessible until you login with your UQ eSpace credentials)
Name Description MIMEType Size Downloads
UQ357205_OA.pdf Full text (open access) application/pdf 695.82KB 0

Author Tang, Yi
Bergmann, Neil W.
Title A hardware scheduler based on task queues for FPGA-based embedded real-time systems
Journal name IEEE Transactions on Computers   Check publisher's open access policy
ISSN 0018-9340
Publication date 2015-05-01
Year available 2015
Sub-type Article (original research)
DOI 10.1109/TC.2014.2315637
Open Access Status File (Author Post-print)
Volume 64
Issue 5
Start page 1254
End page 1267
Total pages 14
Place of publication Piscataway, United States
Publisher Institute of Electrical and Electronics Engineers
Collection year 2016
Language eng
Abstract A hardware scheduler is developed to improve real-time performance of soft-core processor based computing systems. A hardware scheduler typically accelerates system performance at the cost of increased hardware resources, inflexibility and integration difficulty. However, the reprogrammability of FPGA-based systems removes the problems of inflexibility and integration difficulty. This paper introduces a new task-queue architecture to better support practical task controls and maintain good resource scaling. The scheduler can be configured to support various algorithms such as time sliced priority scheduling, Earliest Deadline First and Least Slack Time. The hardware scheduler reduces scheduling overhead by more than 1,000 clock cycles and raises the system utilization bound by a maximum 19.2 percent. Scheduling jitter is reduced from hundreds of clock cycles in software to just two or three cycles for most operations. The additional resource cost is no more than 17 percent of a typical softcore system for a small scale embedded application.
Keyword FPGA
Task scheduling
Priority queue
Real-time systems
Q-Index Code C1
Q-Index Status Confirmed Code
Institutional Status UQ

Document type: Journal Article
Sub-type: Article (original research)
Collections: Official 2016 Collection
School of Information Technology and Electrical Engineering Publications
Version Filter Type
Citation counts: TR Web of Science Citation Count  Cited 1 times in Thomson Reuters Web of Science Article | Citations
Scopus Citation Count Cited 0 times in Scopus Article
Google Scholar Search Google Scholar
Created: Sun, 03 May 2015, 01:16:26 EST by System User on behalf of Scholarly Communication and Digitisation Service