The research described in this thesis was undertaken with the aim of providing a suitable computer architecture for supporting the development and execution of large software systems decomposed into modules according to the information hiding principle. In the course of this work, the author developed two models relevant to the achievement of this aim.
The first model is framed in terms of a memory management and addressing scheme which bases protection on capabilities and overcomes the major memory management and address translation problems found in other capability-based architectures.
The second model modifying an existing this architecture. It arose from the author's practical work in computer (a Hewlett Packard HP2100A) to support proposes a general technique for upgrading relatively primitive computers to support more advanced features, in terms of addressing modes, additional registers, new instructions and virtual memory.
Chapter 1 provides background information which led the author to undertake this research, and explains the structure of the thesis.
Chapter 2 surveys the conventional memory management systems, and describes a number of the more common problems associated with them.
Chapter 3 describes the hardware used by most memory management systems.
Chapter 4 surveys current capability based addressing schemes and highlights their problems.
Chapter 5 describes the new architectural model and shows how it solves the problems raised in earlier chapters.
Chapter 6 addresses the problem of how to implement the new model both cheaply and quickly. In doing so, it develops a general technique which can be used to implement new computer architectures.
Chapter 7 describes a practical implementation of the addressing scheme described in chapter 5 using the technique defined in Chapter 6.
The concluding chapter examines the extent to which the two models proposed in this thesis have been successful and practical.
The two major contributions of this research work are the new addressing model proposed in Chapter 5, and the architectural enhancement model proposed in Chapter 6 .
The new addressing model avoids the two major problems of current capability based computers, namely memory management problems associated with small and large segments, and also address translation problems which arise in systems which make abundant use of segments. The model is shown to be more efficient than the addressing schemes used in other capability systems. Unlike other capability based and conventional computers, it is flexible enough to efficiently implement many different capability addressing structures. Consequently, the software ideas can change and evolve, without affecting the hardware.
The new enhancement technique allows many different architectural enhancements to be implemented and tested as an extension of an existing computer system, and thus allows a full scale evaluation of the ideas to be made. Because the technique allows complex structures to be constructed quickly, accurately and cheaply, it avoids the problems found in many theses which propose new architectures without coming to terms with their practical implications.
In addition to these contributions, during the course of the implementation work, a new address translation unit was devised which, whilst not significantly different in concept, is significantly different in implementation from many other units.