Evaluation of the effects of drain-induced barrier lowering and source-drain punchthrough in MOSFETs

Yu, Mu-chi Lisa (1999). Evaluation of the effects of drain-induced barrier lowering and source-drain punchthrough in MOSFETs B.Sc Thesis, School of Computer Science and Electrical Engineering, The University of Queensland.

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Author Yu, Mu-chi Lisa
Thesis Title Evaluation of the effects of drain-induced barrier lowering and source-drain punchthrough in MOSFETs
School, Centre or Institute School of Computer Science and Electrical Engineering
Institution The University of Queensland
Publication date 1999
Thesis type B.Sc Thesis
Total pages 45
Language eng
Subjects 0906 Electrical and Electronic Engineering
Formatted abstract

In short channel MOSFETs, the depletion regions of the drain and the source diffusions are close to each other resulting in significant field penetration from drain to source. The potential barrier at the source is lowered due to this field penetration. This process is called Drain-Induced Barrier Lowering (DIBL). When the potential barrier lowering is large enough by drain voltage, an enhanced source injection current to the drain depletion region forms. This current is punchthrough current..

The effects of DIBL and source-drain punchthrough are the most important limitations in short channel MOSFET design. In this thesis, measurements of DIBL and numerical analysis of the Poisson equation is performed to match experimental and theoretical results. El-Mansy-Ko model is used to derive a simple solution of the two-dimensional Poisson equation and also the relationship of DIBL and electric field. This solution can be applied for long channel as well as short channel MOSFET. Moreover, the relationship between the threshold shift and the DIBL is discussed in the paper.

The degree of the field penetration that lowers barrier potential depends on several design parameters. Thus, the influence of varying junction depth, increasing oxide thickness and heavier doping on the DIBL effect have been investigated by the computation of the subthreshold current.

Characteristics of the punchthrough mode of device operation have been shown in log ID-VGS and log ID-VDS plots. It involves enhanced injection from the source due to drain-induced source-potential barrier lowering (DIBL).

The results obtained for gate and drain characteristics (log ID-VGS and log ID-VDS) are presented by using the computer program MEDICHI. The drain-induced barrierlowering effect has been discussed for a number of short-channel devices of the 0.6μm MOSFET VLSI technology by using computer numerical simulations.

Keyword MOSFETs
Drain-induced barrier lowering (DIBL)
Source-drain punchthrough
Additional Notes * 4th year electrical engineering theses and information technology abstracts. 1999

Document type: Thesis
Collection: UQ Theses (non-RHD) - UQ staff and students only
Citation counts: Google Scholar Search Google Scholar
Created: Fri, 31 May 2013, 11:35:26 EST by Mr Yun Xiao on behalf of Scholarly Communication and Digitisation Service