Silicon-on-sapphire (SOS) technology, which is a version of the silicon-on-insulator (SOI) technology, has number of advantages including radiation hardness, low power consumption, suitability for high frequency applications and for integration with optoelectronics devices. These are solid advantages which are derived from the material properties of the sapphire substrate. The hetero-structure of silicon-and-sapphire possesses potentials benefiting from the advantages of both constituent materials: silicon is the most extensively investigated and used semiconductor material and it has a well-developed fabrication technology for integrated circuits production; sapphire is a highly insulating material and has a crystal structure closely compatible with single crystal silicon making it a natural choice to grow epitaxial silicon, it also possesses the near ideal optical properties, chemical resistance, mechanical resistance and high thermal conductivity all of which contribute to the advantages of SOS technology mentioned above.
One important phase for the development of the SOS technology directly relevant to this research is the modification of an existing silicon wafer CMOS fabrication tools to process SOS wafers. This work is required for SOS technology to benefit from the established silicon process technologies. Since the existing silicon wafer processing tools are designed to handle silicon wafers, material properties of SOS wafers different from silicon wafers can cause the process to perform differently. To overcome this problem requires processes and/or tool adjustments. The SOS CMOS devices used in this thesis are produced from this modified fabrication line. Author was involved in all aspects the modification works. Some examples from these modification works are presented in this thesis in order to present one of the foundation required to develop SOS technology within the extent that no industrial confidential information is disclosed.
While the SOS hetero-structure has potential to benefit from the properties of both materials, the silicon-on-sapphire interface produces number of phenomena which are not fully understood. Of these phenomena arising from the interface, the work reported in this thesis is an empirical study targeted to understand the mechanisms of the off-state leakage current of fully depleted SOS n-MOSFET’s fabricated on epitaxially grown silicon on sapphire substrate. The research topic is critical to the SOS technology as the suppression of the leakage current is essential to expand the technology into the low power consumption applications and larger scale integrated circuits.
The first part of the research is on the design and the characterizations of a MOS capacitor test structure to electrically access the silicon-to-sapphire interface, often referred to as the back interface. The test structure has a feature to enable the communication with the isolated silicon film of the SOS structure through both majority carrier and minority carrier producing what are effectively quasi-static C-V characteristics at high-frequency (at 100 kHz). The C-V results were explained based on MOS device physics and 2-D device simulations. Correlation between the measured MOSFET off-state leakage current and the measured C-V characteristics indicates that the dominant cause of the off-state leakage is the back interface depletion due to trapped charge at the back interface.
Based on the above understanding, a technique of annealing the SOS film in hydrogen prior to CMOS fabrication to eliminate the back surface depletion is proposed. The n-MOSFET built on the hydrogen annealed SOS film has demonstrated that, (a) the off-state leakage current is reduced to p-n junction leakage level, the lowest leakage current achievable for a MOSFET, (b) the n-MOSFET punch through voltage has more than doubled for transistors with gate length of 0.5 µm when compared with n-MOSFETs fabricated on unannealed SOS film and (c) there is no change in the carrier mobility of the front silicon-silicon dioxide interface, which means that the front channel is not affected. From the SIMS analysis, it was determined that the hydrogen anneal has created a thin aluminium-rich silicon layer at the back interface which is attributed to the out diffusion of aluminium complex from the sapphire substrate. This thin aluminium-rich silicon layer has eliminated the back interface depletion and has pushed up the punch through voltage of n-MOSFETs. The elimination of the back surface depletion is attributed to the creation of the aluminium-rich silicon layer as electrically, it acts as p-type doped silicon film. The increase in the punch-through voltage is attributed to the increased surface recombination velocity at the back interface based on the device simulation studies.
Detailed experimental investigation of the annealing process indicates that both physical thickness of the thin aluminium-rich layer and the surface recombination velocity of the back interface are controllable by changing the annealing conditions i.e., annealing temperature, time and annealing gas ambient. The outcome of this research work is applicable for the commercial production of SOS wafers.