Evaluation and modelling of hot-carrier induced degradation in MOSFETs by gate-to-drain capacitance measurement

Ghodsi, Ramin (1995). Evaluation and modelling of hot-carrier induced degradation in MOSFETs by gate-to-drain capacitance measurement PhD Thesis, School of Computer Science and Electrical Engineering, The University of Queensland.

       
Attached Files (Some files may be inaccessible until you login with your UQ eSpace credentials)
Name Description MIMEType Size Downloads
THE9231.pdf Full text application/pdf 17.55MB 2
Author Ghodsi, Ramin
Thesis Title Evaluation and modelling of hot-carrier induced degradation in MOSFETs by gate-to-drain capacitance measurement
School, Centre or Institute School of Computer Science and Electrical Engineering
Institution The University of Queensland
Publication date 1995
Thesis type PhD Thesis
Supervisor Yew T. Yeow
Total pages 220
Language eng
Subjects 0906 Electrical and Electronic Engineering
Formatted abstract

Hot-carrier degradation in sub-micron n-channel and p-channel MOSFETs is investigated through experimental and numerical simulation study of the effect of spatially distributed trapped carriers and interface states on the small-signal gate-to-drain capacitance. These trapped charges affect the capacitance through their influence on the channel potential profile. A unified model for hot-carrier degradation in n- and p-channel submicron MOSFETs is arrived at by this study. 

The experimental study of trapped charges involved the comparison of the measured gate-to-drain capacitance before and after stressing the device under different bias conditions. These gate-to-drain capacitance results were compared with the corresponding charge pumping, Id-Vd and Id-Vg measurements. 

Models for the hot-carrier induced interface states and trapped carriers were developed. The two dimensional device simulation program MINIMOS was modified to incorporate these models. In particular these modifications allowed the introduction of donor and acceptor interface states with an arbitrary energy distribution in the bandgap and an arbitrary spatial distribution along the channel. The model for interface states also introduced the occupancy calculation using the Shockely-Read-Hall recombination process at the surface. The modified MINIMOS program was used to calculate gate-to-drain capacitance in the presence of these spatially localized interface states and trapped carriers. The effect of the different density and spatial distribution of these trapped charges (trapped carriers and interface states) on the gate-to-drain capacitance was investigated by using these numerical computations. The measurement and numerical simulation results for gate-to-drain capacitance before and after electrical stressing are presented and compared. It is shown that comparison of the measured gate capacitances before and after stress can be used to differentiate between trapped carriers and interface states generated during stress. 

A critical review of hot-carrier effects and degradation in MOSFETs as well as a review of analytical models for small-signal capacitances of MOSFET are presented. 

In conclusion it was found that the trapping of carriers and the generation of interface states are separate processes. For both p-channel and n-channel devices the worst case degradation was found to be due to the trapping of majority carriers and the creation of acceptor interface states, mainly in the upper half of the bandgap. 

Keyword Metal oxide semiconductor field-effect transistors
Additional Notes Spine title: Hot-carrier degradation in MOSFETs

Document type: Thesis
Collection: UQ Theses (RHD) - UQ staff and students only
 
Citation counts: Google Scholar Search Google Scholar
Created: Thu, 29 Nov 2012, 10:30:39 EST by Miss Wendy James on behalf of Scholarly Communication and Digitisation Service