Scalable optical packet switch architecture for low latency and high load computer communication networks

Calabretta, Nicola, Di Lucente, Stefano, Nazarathy, Yoni, Raz, Oded and Dorren, Harmen (2011). Scalable optical packet switch architecture for low latency and high load computer communication networks. In: Marek Jaworski and Marian Marciniak, 2011 13th International Conference on Transparent Optical Networks, ICTON 2011, Proceedings. 13th International Conference on Transparent Optical Networks (ICTON 2011), Stockholm, Sweden, (1-4). 26-30 June 2011. doi:10.1109/ICTON.2011.5971139

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Author Calabretta, Nicola
Di Lucente, Stefano
Nazarathy, Yoni
Raz, Oded
Dorren, Harmen
Title of paper Scalable optical packet switch architecture for low latency and high load computer communication networks
Conference name 13th International Conference on Transparent Optical Networks (ICTON 2011)
Conference location Stockholm, Sweden
Conference dates 26-30 June 2011
Proceedings title 2011 13th International Conference on Transparent Optical Networks, ICTON 2011, Proceedings
Journal name 2011 13th International Conference On Transparent Optical Networks (icton)
Place of Publication Piscataway, NJ, United States
Publisher IEEE
Publication Year 2011
Sub-type Fully published paper
DOI 10.1109/ICTON.2011.5971139
ISBN 9781457708817
9781457708800
ISSN 2161-2056
Editor Marek Jaworski
Marian Marciniak
Start page 1
End page 4
Total pages 4
Collection year 2012
Language eng
Formatted Abstract/Summary
High performance computer and data-centers require PetaFlop/s processing speed and Petabyte storage capacity with thousands of low-latency short link interconnections between computers nodes. Switch matrices that operate transparently in the optical domain are a potential way to efficiently interconnect 1000's of inputs/outputs, complying the end-to-end latency (~1 μs) of these systems. Current rearrangeable non-blocking switches architectures (Benes, Omega, etc..) have a reconfiguration time (expressed in clock-cycles) at most of Mog2(N), N is the number of nodes. Assuming a clock cycle of 1 ns, it follows that the latency requirement cannot be met for N >; 100. Moreover, being the switch disable during this time, the packets are either lost or buffered, limiting the maximum load of the system. In this work we present a new strictly non-blocking switch architecture with a contention resolution sub system. Key point is that the new architecture supports highly distributed control that allows for reduction of the switching time to few nanoseconds regardless the N input/output nodes. Thus, the architecture can meet the latency requirement without limiting the load of the system.
Keyword Optical packet switching
Optical signal processing
Label processor
In-band labels
Q-Index Code E1
Q-Index Status Confirmed Code
Institutional Status Non-UQ

Document type: Conference Paper
Collections: School of Mathematics and Physics
Non HERDC
 
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Created: Fri, 11 May 2012, 10:08:07 EST by Kay Mackie on behalf of Mathematics