VLSI implementation for MPEG-1/Audio Layer III chip : bitstream processor - low power design

Lin, Li-Yang. (2005). VLSI implementation for MPEG-1/Audio Layer III chip : bitstream processor - low power design MPhil Thesis, School of Information Technology and Electrical Engineering, The University of Queensland.

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Author Lin, Li-Yang.
Thesis Title VLSI implementation for MPEG-1/Audio Layer III chip : bitstream processor - low power design
School, Centre or Institute School of Information Technology and Electrical Engineering
Institution The University of Queensland
Publication date 2005
Thesis type MPhil Thesis
Supervisor Dr Postula
Dr Sri Parameswara
Total pages 322
Collection year 2005
Language eng
Subjects 200102 Communication Technology and Digital Media Studies
Formatted abstract

A vast majority of digital recording systems work in roughly the same way and also have similar design principles. An incoming audio signal is fed into an Analogue-to- Digital (A-D) converter. This Analogue-to-Digital converter takes a series of measurements of the incoming audio signal at regular intervals and stores these as digital signals or binary numbers. The binary numbers are then placed onto some kind of storage medium, from which they can be retrieved. Playback performs a simplified reverse form of the encoding process. During the playback process, a Digital-to-Analogue converter is used to convert digital signals back to a very close approximation of the original audio signal, which can be passed to a loudspeaker and heard as sound. 


Space on web servers is limited and can be sometimes costly, and telephone lines simply do not have the necessary bandwidth to allow for the fast transmission of very large files. Moreover, in order to store recordings with excellent sound quality as a file on a computer, the system will use up an enormous amount of storage. To overcome all these problems, a desirable compression is needed to reduce the size of the file as far as possible. 


Anybody who is interested in music and audio can hardly have failed to notice that 'MP3' (MPEG-1/Audio Layer III) is an increasingly popular media buzzword. MPEG- 1/Audio Layer III is the most controversial and popular computer sound format ever. It represents a revolution in the compression technology and music business. For the first time listeners can store, play, and manipulate their favourite music on a personal computer with small "CD-quality" music files by using the new MPEG-1/Audio Layer III format. 


Chip sets, consisting of several signal processors and a digital-to-analogue converter, form the heart of the increasingly popular MP3 players which can record and play back compressed music from the Internet or other sources. A Digital-to- Analogue converter is used for analogue audio output that has been optimized for audio applications. As a result of increasing prominence of MP3 players/portable battery operated systems and the need to limit power consumption in very-high density; VLSI chips have led to rapid and active developments in low-power design. The requirement for low power consumption must be met along with demanding goals of high chip density and high throughput, therefore the need for low power design has became a major issue in high performance MP3 playback systems.


The topic for this thesis is the design and implementation of a microprocessor with low power consumption to be applied in an MPEG-1/Audio Layer III decoder. The Layer III decoding scheme is a complex compound of algorithms ranging from digital signal processing to data unpacking and interpretation. However, only parts of the bitstream processor will be implemented within the chip in this project, an audio signal processor can decode MPEG-1/Audio Layer III in real time. 


The target design of the 16 bit MPEG-1/Audio Layer III bitstream processor operates at a clock frequency approximately 15 MHz and is capable of processing a Layer III bitstream with 3.1 million instructions per second. The skeleton/architecture of this MPEG-1/Audio Layer III bitstream processor adopts the design from the Institute of Electronic Systems - Aalborg University. Several low power methods /algorithms have been incorporated into this project and new controllers have been designed. The implementation of the bitstream processor went through a series of design simulations to verify its functionality is consistent with the predefined specifications. 


The design is synthesized and optimized by both Leonardo Spectrum CAD tool with AMI 0.5-micro technology and Xilinx with Virtex technology. The reason for synthesizing the design with both AISC and FPGA technology is due to unavailability of the ASIC power analysis tool in the department. Xpower, the FPGA power analysis tool provided by Xilinx is used to measure the overall power consumption of the design. The bitstream processor compares the power consumption with other existing commercial MPEG-1/Audio Layer III decoders. The bitstream processor was not fabricated for actual hardware testing due to time and budget constraints. Future research direction in relation to the lower power design is also discussed. 

Keyword MP3 (Audio coding standard)
Sound -- Recording and reproducing -- Digital techniques -- Standards
Integrated circuits -- Very large scale integration

Document type: Thesis
Collection: UQ Theses (RHD) - UQ staff and students only
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Created: Mon, 12 Mar 2012, 10:33:51 EST by Bekti Mulatiningsih on behalf of The University of Queensland Library