The fabrication of metallic nanotransistors

Cheng, H. H., Siaw, J. K. and Alkaisi, M. M. (2005). The fabrication of metallic nanotransistors. In: Aleksandar D. Rakic and Yew Tong Yeow, 2004 Conference On Optoelectronic And Microelectronic Materials And Devices: COMMAD 04 Proceedings. COMMAD 2004: Conference on Optoelectronic and Microelectronic Materials and Devices, Brisbane, Australia, (121-124). 8-10 December 2004. doi:10.1109/COMMAD.2004.1577507


Author Cheng, H. H.
Siaw, J. K.
Alkaisi, M. M.
Title of paper The fabrication of metallic nanotransistors
Conference name COMMAD 2004: Conference on Optoelectronic and Microelectronic Materials and Devices
Conference location Brisbane, Australia
Conference dates 8-10 December 2004
Convener Institute of Electrical and Electronics Engineers (IEEE)
Proceedings title 2004 Conference On Optoelectronic And Microelectronic Materials And Devices: COMMAD 04 Proceedings
Place of Publication Piscataway, NJ, U.S.A.
Publisher Institute of Electrical and Electronics Engineers (IEEE)
Publication Year 2005
Sub-type Fully published paper
DOI 10.1109/COMMAD.2004.1577507
ISBN 9780780388208
0780388208
ISSN 1097-2137
Editor Aleksandar D. Rakic
Yew Tong Yeow
Start page 121
End page 124
Total pages 3
Language eng
Formatted Abstract/Summary
Extensive research studies have been devoted into the field of scaling down transistor size for ultra high density integrated circuits over the last three decades. It has been suggested that for the smallest possible scale of MOS transistor channel, a channel conductance close to that of a metal is required. Metallic nanotransistors are based on field effect transistor made from metallic nanowires. This type of transistor operates by governing the flow of electrons through a narrow channel. In the fabrication of metallic nanotransistors, an electron beam lithography process has been developed to fabricate structures at the sub30 nm scale using silver n a no wires on SiN substrate. The single pass line exposure technique in electron beam lithography has been employed to define patterns of transistor structure as small as 20.2 n m dimensions. This paper details the design and fabrication techniques of metallic nanotransistors. The limiting issues for writing sub30 nm structures using EBL such as the charging effect of insulating materials, the proximity effects, and the single pass exposures are discussed.
© 2005 IEEE
Subjects 0906 Electrical and Electronic Engineering
0205 Optical Physics
Keyword Metallic FET
Y-Branch
EBL
Nanotransistor
Q-Index Code EX

 
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Created: Mon, 29 Mar 2010, 22:13:07 EST by Jon Swabey on behalf of Aust Institute for Bioengineering & Nanotechnology