The fabrication and characterisation of metallic nanotransistors

Cheng, H. H., Andrew, C. N. and Alkaisi, M. M. (2006). The fabrication and characterisation of metallic nanotransistors. In: Microelectronic Engineering. Proceedings of: Micro- and Nano-Engineering MNE 2005. MNE 2005: 31st International Conference on Micro- and Nano-Engineering 2005, Vienna, Austria, (1749-1752). 19-22 September 2005. doi:10.1016/j.mee.2006.01.238


Author Cheng, H. H.
Andrew, C. N.
Alkaisi, M. M.
Title of paper The fabrication and characterisation of metallic nanotransistors
Conference name MNE 2005: 31st International Conference on Micro- and Nano-Engineering 2005
Conference location Vienna, Austria
Conference dates 19-22 September 2005
Proceedings title Microelectronic Engineering. Proceedings of: Micro- and Nano-Engineering MNE 2005   Check publisher's open access policy
Journal name Microelectronic Engineering   Check publisher's open access policy
Place of Publication Amsterdam, Netherlands
Publisher Elsevier BV
Publication Year 2006
Sub-type Fully published paper
DOI 10.1016/j.mee.2006.01.238
ISSN 0167-9317
1873-5568
Volume 83
Issue 4-9
Start page 1749
End page 1752
Total pages 4
Language eng
Formatted Abstract/Summary
Enormous research studies and funding have been invested into the field of transistor miniaturisation for the last five decades. For the smallest possible MOS transistor, a channel conductance close to that of a metal has been suggested [S.V. Rotkin, K. Hess, Principles of metallic field effect transistor, in: Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, vol. 2, 2004, pp. 37–40.]. Metallic nanotransistors are promising candidates that might serve as an alternative solution for overcoming the shrinking limit of conventional MOS structures. This type of transistor operates similarly to depletion type MOSFET by governing the flow of electrons through a narrow channel made from metallic nanowire. In the fabrication of metallic nanotransistors, an electron beam lithography process has been developed to fabricate structures at the sub 30 nm scale using silver nanowires on Si3N4 substrate. The one-dimensional structure and the use of single material for the construction of the metallic transistors also allow the use of advanced nanoimprint technology for rapid and economic fabrication. This paper details the design, fabrication and characterisation techniques for two structures of all metal nanotransistors.
© 2006 Elsevier B.V. All rights reserved.
Subjects 0906 Electrical and Electronic Engineering
Keyword Metallic nanotransistor
Electrostatic transistor
Y-branch
Q-Index Code EX

 
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Created: Mon, 29 Mar 2010, 21:19:19 EST by Jon Swabey on behalf of Aust Institute for Bioengineering & Nanotechnology