Analysis and Architectures for Bang-bang Phase Locked Loops

Mr Michael Chan (2008). Analysis and Architectures for Bang-bang Phase Locked Loops PhD Thesis, School of Information Technol and Elec Engineering, The University of Queensland.

       
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Author Mr Michael Chan
Thesis Title Analysis and Architectures for Bang-bang Phase Locked Loops
School, Centre or Institute School of Information Technol and Elec Engineering
Institution The University of Queensland
Publication date 2008-04
Thesis type PhD Thesis
Supervisor Dr Adam Postula
Total pages 161
Total black and white pages 161
Subjects 290000 Engineering and Technology
Formatted abstract The topic of this thesis is bang-bang phase locked loops. In the first half of this work,
focus is given to the non-linear dynamics of bang-bang PLLs operating in the far from
lock region. This region of operation is characterised by a very non-linear and time
variant phenomena called cycle slipping, which makes analysis difficult. Designers of
bang-bang PLLs are consequently very reliant on simulation tools in order to
determine bang-bang PLL behaviour when far from lock.
A better understanding of this region is important for two reasons. Firstly, behaviour
in this region determines PLL locking range (capture range) and locking time, which
are both important components of a PLLs performance. Secondly, bang-bang PLLs
are increasingly becoming the PLL architecture of choice in systems operating near the
speed limits of current technology.
In this work, the transient response for the second order bang-bang phase locked loop
is derived. From this response, the amount of time the PLL spends in the far from lock
region can be predicted, which allows for calculation of PLL locking time. The
locking range or capture range for the second order bang-bang PLL is also derived in
this work. Both of these results are verified by extensive simulation.
In the second half of this thesis, three different bang-bang PLL architectures aimed at
improving far from lock performance are presented. The first architecture employs a
novel method to determine whether a PLL is far from lock, or close to lock.
Depending on distance from lock, PLL loop gain is scaled in order to reduce lockingtime. The conditions under which the capture range of this architecture can be
improved are also explored.
The second architecture employs a small or large loop gain depending on whether the
PLL’s phase error is less than or greater π / 2 respectively. The advantage of this
architecture is that the two loop gains can be used to independently optimize both
capture range and jitter when in lock. The capture range for this system is derived and
it is shown that capture range depends predominantly on the PLL’s outer loop gain,
thus freeing inner loop gain to control PLL dynamics when in lock
The final PLL architecture presented is based on a new bang-bang phase detector
structure. This phase detector assumes a VCO that generates clock phases spaced 90
degrees apart, and it attempts to align a PLLs reference signal with the most suitable
clock phase. The scheme presented ensures that PLL phase error is maintained under
90 degrees, thus cycle slipping cannot occur in the PLL. This results in a massive
improvement to PLL locking time, and significant improvements to PLL capture
range. Performance when in lock for this system is similar to the commonly employed
Alexander phase detector.

 
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Created: Thu, 06 Nov 2008, 23:29:38 EST by Mr Michael Chan on behalf of Library - Information Access Service