A New Architecture for Virtual Private Networking with Reconfigurable System-on-Chip Technology

Wee, Chin (2007). A New Architecture for Virtual Private Networking with Reconfigurable System-on-Chip Technology PhD Thesis, School of Information Technology and Electrical Engineering , University of Queensland.

       
Attached Files (Some files may be inaccessible until you login with your UQ eSpace credentials)
Name Description MIMEType Size Downloads
n01front_wee.pdf n01front_wee.pdf application/pdf 209.85KB 2
n02content_wee.pdf n02content_wee.pdf application/pdf 1.03MB 5
Author Wee, Chin
Thesis Title A New Architecture for Virtual Private Networking with Reconfigurable System-on-Chip Technology
School, Centre or Institute School of Information Technology and Electrical Engineering
Institution University of Queensland
Publication date 2007
Thesis type PhD Thesis
Supervisor Dr Peter Sutton
Abstract/Summary As Internet connectivity becomes ubiquitous, so does the need for network safety and security. The major concerns are to keep private data secure from unwanted access and this can be done using a virtual private network (VPN). Current VPN technologies based on embedded systems with software-only algorithm implementations are difficult to scale to the network speeds and algorithmic complexity required. A solution to this problem will be proposed in this research project using Field Programmable Gate Array (FPGA) based reconfigurable Systemon- Chip (rSoC) technology A 3DES-CBC core with key generator that achieves more than 100Mbit/s of encryption or decryption while occupying about 608 slices in a Xilinx FPGA is presented. This will allow the 3DES core to be implemented in much smaller FPGAs or put together with other cores to form the rSoC on the same chip. Coupling the flexibility of the rSoC and hardware cipher cores can be an effective solution to the current real world requirement for a flexible and affordable VPN platform. The accessible performance of hardware cryptographic accelerator cores after integration to a reconfigurable System-on-Chip is a relatively unexplored area. There is also little work done on a stream aware cipher core for reconfigurable systems. This thesis presents a novel architecture, the Multi Stream Cipher Architecture (MSCA), which allows a cipher core to operate on multiple cipher streams without software context switching. This architecture will also allow a single point of interface for multiple different cipher cores to be integrated with the reconfigurable System-on-Chip. The architecture is integrated to the MicroBlaze soft-processor running the uClinux operating system. Different access methods in uClinux are also examined in this thesis. A user space device driver has been written in uClinux to access the cryptographic architecture. It can achieve a throughput of 45Mbps. The kernel space device driver has also been written in uClinux to run on the Open Crypto Framework (OCF). This driver can achieve a maximum throughput of 12Mbps but offers various other benefits compared to the user space driver. A popular VPN application for PC-based Linux systems has also been ported to uClinux and the performance tested. Based on the results of these evaluations, this thesis also examines the implications of using different access methods specifically their performance and accessibility.

 
Citation counts: Google Scholar Search Google Scholar
Access Statistics: 315 Abstract Views, 7 File Downloads  -  Detailed Statistics
Created: Fri, 21 Nov 2008, 16:21:07 EST