Self-checking synchronous controller design

Kia, S. M. and Parameswaran, S. (1999) Self-checking synchronous controller design. IEE Proceedings: Computers and Digital Techniques, 146 1: 9-12. doi:10.1049/ip-cdt:19990243


Author Kia, S. M.
Parameswaran, S.
Title Self-checking synchronous controller design
Journal name IEE Proceedings: Computers and Digital Techniques   Check publisher's open access policy
ISSN 1350-2387
1751-861X
Publication date 1999-01
Sub-type Article (original research)
DOI 10.1049/ip-cdt:19990243
Volume 146
Issue 1
Start page 9
End page 12
Total pages 4
Editor E. L. Dagless
G. Brebner
Place of publication Stevenage, Hertfordshire, U.K.
Publisher IEE
Collection year 1999
Language eng
Subject C1
671203 Modules-other processes
290903 Other Electronic Engineering
Formatted abstract
Efficient models are introduced for totally self-checking/code disjoint (TSC/CD) and strongly fault-secure/strongly code disjoint (SFS/SCD) synchronous controller models. These models are based on two low-cost, modular, TSC edge-triggered and error-propagating CD flip-flops. Properties of the proposed synchronous controller models are proven. The design procedure for these models and their proper applications are explained
© IEE, 1999
Q-Index Code C1

Document type: Journal Article
Sub-type: Article (original research)
Collection: School of Information Technology and Electrical Engineering Publications
 
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Created: Tue, 10 Jun 2008, 14:33:30 EST