Designing Agent Chip

Insu Song (2007-11). Designing Agent Chip PhD Thesis, School of Information Technology and Electrical Engineering, The University of Queensland.

Document type: Thesis
Collection: UQ Theses Collection (MPhil and PhD)
 
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n32368233_phd_abstract.pdf n32368233_phd_abstract.pdf application/pdf 35.19KB 4
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n32368233_phd_totalthesis.pdf n32368233_phd_totalthesis.pdf application/pdf 2.30MB 6


Author(s) Insu Song
Thesis Title Designing Agent Chip
School, Centre or Institute School of Information Technology and Electrical Engineering
Institution The University of Queensland
Publication date 2007-11
Thesis type PhD Thesis
Supervisor(s) Colomb, Robert M.
Governatori, Guido
Subjects 290000 Engineering and Technology
280000 Information, Computing and Communication Sciences
Formatted abstract This thesis provides a new approach to designing smart electronic chips called agent chips. It pro-vides a layered argumentation system for specifying smart systems and an automated method for synthesizing smart electronic chips from an agent specification in the layered argumentation sys-tem. The layered argumentation system is a consistent instantiation of a logic based argumentation system extended with Brooks’subsumption concept, varying degrees of confidence, and fuzzy op¬erators. The layered argumentation system provides a conceptual and behavioral decomposition of smart systems into varying degrees of confidence or competence. Particularly, the thesis provides a new method of compiling the layered argumentation system into hardware description formats, such as RTL¬VHDL(Register Transfer Level–VLSI Hardware Description Language)or RTL¬Verilog, which is synthesized using computer¬assisted tools to develop ASIC(Application Specific Integrated Circuits) masks or FPGA (Field Programmable Gate Arrays) configurations. To prevent abnormal behaviors that can be caused by loops in the theories of layered argumentation system, it provides algorithms for detecting loops and algorithms for removing loops preserving intensional knowledge. Experiments generating digital circuit description from layered argumentation system are reported. Finally, tools for generating general logic programs and hardware description from layered argu¬mentation theories are provided.
 
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