A Hybrid Reconfigurable Cluster-on-Chip Architecture with Message Passing Interface for Image Processing Applications

Syed, Irfan, Williams, John A. and Bergmann, Neil W. (2007). A Hybrid Reconfigurable Cluster-on-Chip Architecture with Message Passing Interface for Image Processing Applications. In: Bertels, K., Najir, W, Van Genderen, A. and Vassiliadis, S, Proceedings 2007 International Conference on Field-Programmable Logic and Applications. 2007 International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam, The Netherlands, (609-612). 27 - 29 August, 2007.


Author Syed, Irfan
Williams, John A.
Bergmann, Neil W.
Title of paper A Hybrid Reconfigurable Cluster-on-Chip Architecture with Message Passing Interface for Image Processing Applications
Conference name 2007 International Conference on Field Programmable Logic and Applications (FPL 2007)
Conference location Amsterdam, The Netherlands
Conference dates 27 - 29 August, 2007
Convener Bertels, K.
Proceedings title Proceedings 2007 International Conference on Field-Programmable Logic and Applications
Journal name 2007 International Conference On Field Programmable Logic and Applications, Proceedings, Vols 1 and 2
Place of Publication Piscataway, NJ, USA
Publisher IEEE
Publication Year 2007
Sub-type Fully published paper
DOI 10.1109/FPL.2007.4380728
ISBN 1-4244-1060-6
Editor Bertels, K.
Najir, W
Van Genderen, A.
Vassiliadis, S
Start page 609
End page 612
Total pages 4
Collection year 2008
Language eng
Abstract/Summary We demonstrate a hybrid reconfigurable cluster-on-chip architecture with a cross-platform Message Passing Interface (MPI), a cross-platform parallel image processing library and a sample application. We describe the system, network architecture, MPI library and the parallel image processing library implementations. We validate the performance, scalability and suitability of MPI as a software interface to enable cross-platform application parallelism on reconfigurable hybrid cluster-on-chip systems and desktop cluster systems. The presented results are promising, showing the suitability, scalability and performance of parallelisation of image processing algorithms with a cross-platform MPI implementation.
Subjects 291605 Processor Architectures
671201 Integrated circuits and devices
E1
Q-Index Code E1
Q-Index Status Confirmed Code

 
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