A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip

Bergmann, Neil, Waldeck, Peter and Williams, John (2003). A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip. In: Badawy, Wael and Ismail, Yehya, Proceedings of the Third IEEE International Workshop on System-on-Chip for Real-Time Applications. IEEE International Workshop on System-on-Chip for Real-time Applications, Calgary, Alberta, Canada, (112-115). June 30 - July 2.

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Author Bergmann, Neil
Waldeck, Peter
Williams, John
Title of paper A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip
Conference Paper Type Fully Published Paper
Conference name IEEE International Workshop on System-on-Chip for Real-time Applications
DOI 10.1109/IWSOC.2003.1213017
Conference location Calgary, Alberta, Canada
Conference dates June 30 - July 2
Proceedings title Proceedings of the Third IEEE International Workshop on System-on-Chip for Real-Time Applications
Journal name 3rd Ieee International Workshop On System-On-Chip for Real-Time Applications, Proceedings
Editor Badawy, Wael
Ismail, Yehya
Place published Los Alamitos, CA
Publisher IEEE Computer Society
Publication date 2003
Volume number 1
ISBN 0-7695-1944-X
Start page 112
End page 115
Total pages 4
Language eng
Abstract/Summary The new technology of reconfigurable System-on-Chip is shown to be a good match to the requirements of real-time embedded systems. In particular, the judicious use of specialised data processing peripherals can reduce the CPU load significantly and greatly ease the task of guaranteeing that real-time deadlines are met in complex multi-processing real-time systems. A catalog of other possible uses for the reconfigurable logic resources on such a chip which can assist in improving real-time system performance is also presented.
Subjects 290903 Other Electronic Engineering
280304 Operating Systems
291605 Processor Architectures
289999 Other Information, Computing and Communication Sciences
E1
Keyword reconfigurable system-on-chip
real-time
esgweb-research-egret
custom hardware processor architecture
References [1] Xilinx, "Xilinx FPGA Product Tables", on-line at www.xilinx.com [2] Triscend, "A7 Configurable System-on-Chip" on-line at www.triscend.com [3] Altera, "About Excalibur Embedded Processor Solutions" on-line at www.altera.com [4] "FPSLIC - Field Programmable System Level Integrated Circuits" at www.atmel.com [5] G. Berry, "The Esterel v5 Language Primer" at ftp://ftp.esterel.org/esterel/pub/papers/primer.pdf [6] N. W. Bergmann, G. Brebner, and J.P. Gray, "Reconfigurable Computing and Reactive Systems" Proceedings of the Australasian Workshop on Parallel and Real-Time Systems: PART '00, Newcastle, November, 2000 [7] "M68HC11 Family", on-line at e-www.motorola.com [8] K. Tindell, "Deadline Monotonic Analysis", Embedded System Programming, 13(6), June 2000 [9] N.W. Bergmann, J.A. Williams, Peter Waldeck, "Egret: A Flexible Platform for Real-Time Reconfigurable Systems-on-Chip", Engineering of Reconfigurable Systems and Algorithms: ERSA '03, Las Vegas, June 2003.
Q-Index Code E1

 
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Created: Fri, 20 Feb 2004, 10:00:00 EST by John A Williams on behalf of School of Information Technol and Elec Engineering