On a photonic bus architecture that incorporates wavelength multiplexing and reuse for reconfigurable computers

Boros, Vince Elias (2004). On a photonic bus architecture that incorporates wavelength multiplexing and reuse for reconfigurable computers PhD Thesis, School of Information Technology and Electrical Engineering, The University of Queensland.

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Author Boros, Vince Elias
Thesis Title On a photonic bus architecture that incorporates wavelength multiplexing and reuse for reconfigurable computers
School, Centre or Institute School of Information Technology and Electrical Engineering
Institution The University of Queensland
Publication date 2004
Thesis type PhD Thesis
Supervisor Dr. Aleksandar Rakic
Sri Parameswaran
Total pages 286
Collection year 2004
Language eng
Subjects L
291702 Optical and Photonic Systems
700302 Telecommunications
Formatted abstract

In this document I present an argument, design and model for a photonic computer bus, scalable through wavelength-division multiple access (WDMA) and space-division multiple access (SDMA). I present designs and models for fast and small optoelectronic transceivers at the bus endpoints. 


The architecture has application to reconfigurable, heterogeneous, multiprocessor systems. The photonic bus supports communication among many modules. Each module consists of a processor, with its associated local memory and glue logic; an array of photodiodes and receiver circuits; and an array of vertical-cavity surface-emitting lasers (VCSELs) and transmitter circuits. Each VCSEL in a module transmits the signal of one electrical line to a subset of the system's modules over an optical link. The wavelength of a link signal identifies the transmitting module. A bit sequence in the signal identifies the receiving module. 


The design of the present architecture yields an optoelectronic bus power-limited to 28 modules per WDMA link. Scaling of the system beyond 28 modules is achieved through SDMA, by adding additional optical links in parallel to reuse wavelengths. 


Mathematical models, suitable for system-level applications, cover the characteristics of multiple-quantum-well VCSELs, p-i-n photodiodes, complementary metal-oxide-semiconductor (CMOS) superbuffer-drivers and CMOS transimpedance amplifiers and inverters. 


Single-stage photodiode receivers, capable of amplifying a 13.5 µW optical signal, have a small-signal bandwidth of 1.3 GHz, and VCSEL transmitters are capable of 2.9 GHz, permitting a bit-rate exceeding 1 Gb/s on a single link. A system containing 145 modules, each with 128 electrical signal lines, achieves an aggregate bit-rate in excess of 18.5 Tb/s on the optical bus. The optical links each achieve a bit error rate significantly less than 10-15


Electrical power dissipation by the receivers and transmitters totals 7 W per module and 1 kW for the whole system, in a 145-module 6-link system, with 128 electrical signal lines per module driven onto the photonic bus. In a system containing 40 modules, the system electrical power dissipation reduces to 100 W. 


For applications where power usage is the overriding concern, or in very large-scale systems, I develop a variation of the bus architecture. The variant, while increasing the complexity of the optical blocks, permits a concurrent point-to-point use of the photonic bus.

Keyword Computer architecture
Wavelength division multiplexing
Optoelectronic devices -- Design and construction
Multiprocessors -- Design and construction
Additional Notes

Variant title: Photonic bus architecture

Document type: Thesis
Collection: UQ Theses (RHD) - UQ staff and students only
Citation counts: Google Scholar Search Google Scholar
Created: Fri, 24 Aug 2007, 18:27:44 EST