An FPGA architecture for improved arithmetic performance

Rajagopalan, Kamal. (2001). An FPGA architecture for improved arithmetic performance Master's Thesis, School of Computer Science and Electrical Engineering, The University of Queensland.

Author Rajagopalan, Kamal.
Thesis Title An FPGA architecture for improved arithmetic performance
School, Centre or Institute School of Computer Science and Electrical Engineering
Institution The University of Queensland
Publication date 2001
Thesis type Master's Thesis
Supervisor P. Sutton
Total pages 108
Collection year 2002
Language eng
Subjects L
291601 Arithmetic and Logic Structures
671201 Integrated circuits and devices
Keyword Programmable array logic
Field programmable gate arrays

Document type: Thesis
Collection: UQ Theses - Citation only
 
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Created: Fri, 24 Aug 2007, 17:53:42 EST