Characterization of hot-carrier induced degradation via small-signal characteristics in mosfets

Lau, Mei Po Mabel (2002). Characterization of hot-carrier induced degradation via small-signal characteristics in mosfets PhD Thesis, School of Computer Science and Electrical Engineering, The University of Queensland.

       
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Author Lau, Mei Po Mabel
Thesis Title Characterization of hot-carrier induced degradation via small-signal characteristics in mosfets
School, Centre or Institute School of Computer Science and Electrical Engineering
Institution The University of Queensland
Publication date 2002
Thesis type PhD Thesis
Supervisor Yew Tong Yeow
Total pages 170
Collection year 2002
Language eng
Subjects L
290902 Integrated Circuits
671201 Integrated circuits and devices
Formatted abstract Hot-carrier reliability and device parameter extraction have become two major issues with continued size reduction and changes in structure for modem MOSFETs. Hot-carrier induced damages remain a reliability concern despite lowering of supply voltage and the introduction of hot-carrier resistant devices through drain engineering. As for device parameter extraction, established drain current based methods are starting to become limited for deep submicron devices.

A study on the small-signal characteristics of the drain-to-substrate junction of n- and p-channel MOSFETs configured as a gated diode to investigate hot-carrier induced degradation is presented. The small-signal admittance Ydb across the drain-to-substrate junction consists of the drain-to-substrate conductance Gdb and the drain-to-substrate capacitance Cdt. Based on both experimental and simulation results, it is established that similar to the dc gated-diode measurement, this technique uses the edge of the depletion region as a pointer to detect the presence and spatial distribution of hot-carrier induced interface states. Gdb is capable of detecting midgap states acting as recombination centers like the dc gated-diode current, while change in Cdb after stress reflects presence of ionized interface states and oxide trapped charges. The advantage of using Ydb is that complementary information on hot-carrier induced damages can be obtained with a single measurement. Also, it is shown to be very sensitive in detecting damages at the gate-to-drain overlap region.

The before and after stress experimental Cdb and Gdb curves are compared after non-uniform and uniform electrical stress. It is concluded that the hot-carrier induced damages are localized near the drain region after non-uniform stress. In n-channel MOSFET, these damages are observed to be mainly acceptor-like interface states, while, they are seen to be trapped electrons in p-channel MOSFET. On the other hands, after uniform electrical stress, the hot-carrier induced damages are distributed along the channel. The induced damages are trapped electrons in n-channel device and trapped holes in p-channel device.

The spatial distribution of hot-carrier induced interface states is extracted by modeling its distribution profile with two-dimensional numerical simulation to fit the after stress Cdb curve. The extracted profile is verified by incorporating it back in the simulated device to simulate the post-degradation I-V characteristics and compare with the experimental results.

Also, a new threshold voltage VT extraction method based on the gate-to-substrate capacitance Cgb is proposed. It does not require dc current to flow between the drain and source and thus eliminating the effects of source and drain series resistances. A symmetrical potential profile is also retained across the channel during the extraction measurement. With these advantages, this new method should be able to extract a more precise VT and both experimental and simulation results are compared with results obtained using the linear extrapolation method.

Keyword Metal oxide semiconductor field-effect transistors

Document type: Thesis
Collection: UQ Theses (RHD) - UQ staff and students only
 
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Created: Fri, 24 Aug 2007, 17:51:41 EST