Hot-carrier degradation in sub-micron n-channel and p-channel MOSFETs is investigated through experimental and numerical simulation study of the effect of spatially distributed trapped carriers and interface states on small-signal gate capacitances measured at room and cryogenic temperatures.
A critical review of hot-carrier effects and degradation in MOSFETs as well as a review of analytical models and measurement technique for small-signal gate capacitances of MOSFETs are presented. The concept of using the gate capacitances of MOSFETs to evaluate the hot-carrier generated interface states and oxide trapped charges are investigated in detail and applied in experimental devices. A new method for extracting the spatial distribution of oxide trapped charge through gate-to-substrate capacitance measurement is proposed. Also an analytical model for gate-to-drain capacitance degradation is arrived at by this study.
The experimental aspect of this study involved the comparison of the measured gate capacitances at room and cryogenic temperatures for before and after electrically stressing the device. These gate capacitance results from different hot-carrier injection modes providing broad information on the nature of degradation mechanisms involved. Measurement at different temperatures allows different portions of the silicon bandgap to be sampled, therefore making it effective in distinguishing the degradation effects due to oxide trapped charges and interface traps. In conclusion it was found that the degradation was mostly due to the generation of interface states above the LDD region and the trapping of majority carriers. For n-channel MOSFETs, the major degradation mechanism is due to the generation of acceptor-type interface states in the top half of the bandgap. Hole trapping only becomes significant when the transverse field is sufficiently high during stress and these trapped holes are highly localised in a sharp peak near the stressed junction. For p-channel MOSFETs, electron trapping is the major degradation mechanism. These electron trapped charges are widely distributed with the peak located very close to the gate edge. Also in all stress conditions, there are relatively few interface states generated as compared to trapped electrons and they were found to be donor states at the bottom half of bandgap. In general, hot electrons are more likely to be injected and trapped in gate oxide as compared to hot holes while the presence of hot holes generates more interface states.
For the first time, an analytical model for hot-carrier induced gate-to-drain capacitance degradation is developed and validated by means of 2-D numerical simulation. In this modeling, mobility reduction, change in gate oxide charge and series resistant degradation caused by hot-carrier induced trapped center and the gradual channel approximation were employed. The use of all these parameters for device degradation modeling is new and essential for future sub-micron MOSFETs. This model improves the state of art of capacitive characterization methods. It provides a link between the electrical characteristics of a degraded device and its physical damages. Therefore, it is a vital tool for the study of hot-carrier induced device degradation mechanisms and it also improves the development of the device degradation model for circuit's reliability simulation.