A real-time asymmetric multiprocessor-reconfigurable system-on-chip architecture

Xie, Xin, Williams, John A. and Bergmann, Neil W. (2006). A real-time asymmetric multiprocessor-reconfigurable system-on-chip architecture. In: A. Hariz, Microelectronics, MEMs and Nanotechnology. Microelectronics, MEMs and Nanotechnology, Brisbane, Australia, (603508.1-603508.12). 11-14 December, 2005.


Author Xie, Xin
Williams, John A.
Bergmann, Neil W.
Title of paper A real-time asymmetric multiprocessor-reconfigurable system-on-chip architecture
Conference Paper Type Fully Published Paper
Conference name Microelectronics, MEMs and Nanotechnology
DOI 10.1117/12.638216
Conference location Brisbane, Australia
Conference dates 11-14 December, 2005
Proceedings title Microelectronics, MEMs and Nanotechnology   Check publisher's open access policy
Journal name Microelectronics: Design, Technology, and Packaging II   Check publisher's open access policy
Editor A. Hariz
Place published USA
Publisher The International Society for Optical Engineering
Publication date 2006
Volume number 6035
ISBN 0-8194-6066-4
ISSN 0277-786X
Start page 603508.1
End page 603508.12
Total pages 12
Collection year 2006
Language eng
Abstract/Summary We propose an asymmetric multi-processor SoC architecture, featuring a master CPU running uClinux, and multiple loosely-coupled slave CPUs running real-time threads assigned by the master CPU. Real-time SoC architectures often demand a compromise between a generic platform for different applications, and application-specific customizations to achieve performance requirements. Our proposed architecture offers a generic platform running a conventional embedded operating system providing a traditional software-oriented development approach, while multiple slave CPUs act as a dedicated independent real-time threads execution unit running in parallel of master CPU to achieve performance requirements. In this paper, the architecture is described, including the application / threading development environment. The performance of the architecture with several standard benchmark routines is also analysed.
Subjects E1
291601 Arithmetic and Logic Structures
671202 Modules-special and attached processors
Q-Index Code E1
Institutional Status UQ

 
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Created: Thu, 23 Aug 2007, 22:23:05 EST