Modelling the effects of interface traps on scanning capacitance microsopy dC/dV measurement

Hong, Y. D. and Yeow, T.Y.T. (2005). Modelling the effects of interface traps on scanning capacitance microsopy dC/dV measurement. In: A. D. Rakic and Y. T. Yeow, 2004 Conference on Optoelectronic and Microelectronic Materials and Devices Proceedings. 2004 Conference on Optoelectronic and Microelectronic Material, Brisbane, Australia, (149-152). 8-10 December 2004. doi:10.1109/COMMAD.2004.1577514


Author Hong, Y. D.
Yeow, T.Y.T.
Title of paper Modelling the effects of interface traps on scanning capacitance microsopy dC/dV measurement
Conference name 2004 Conference on Optoelectronic and Microelectronic Material
Conference location Brisbane, Australia
Conference dates 8-10 December 2004
Proceedings title 2004 Conference on Optoelectronic and Microelectronic Materials and Devices Proceedings
Place of Publication Piscataway, NJ, USA
Publisher IEEE
Publication Year 2005
Sub-type Fully published paper
DOI 10.1109/COMMAD.2004.1577514
ISBN 0780388208
Editor A. D. Rakic
Y. T. Yeow
Volume 2005
Start page 149
End page 152
Total pages 4
Collection year 2005
Language eng
Abstract/Summary Scanning capacitance microscopy (SCM) measurement is a proposed tool for dopant profile extraction for semiconductor material. The influence of interface traps on SCM dC/dV data is still unclear. In this paper we report on the simulation work used to study the nature of SCM dC/dV data in the presence of interface traps. A technique to correctly simulate dC/dV of SCM measurement is then presented based on our justification. We also analyze how charge of interface traps surrounding SCM probe would affect SCM dC/dV due the small SCM probe dimension.
Subjects E1
290900 Electrical and Electronic Engineering
671401 Scientific instrumentation
Keyword Component
SCM
Scanning capacitance microscopy
Interface traps
Modeling
Q-Index Code E1
Q-Index Status Provisional Code
Institutional Status UQ

 
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Created: Thu, 23 Aug 2007, 21:04:43 EST