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Tseng, I-Lun and Postula, Adam (2004). A Layout-Aware Circuit Sizing Model Using Parametric Analysis. In: Y. Takeuchi, Proceedings of the Workshop on Synthesis and System Integration of Mixed Information Technologies. The 12th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI'04), Kanazawa, Japan, (235-240). 18-19 October, 2004. 1653 347
Tseng, I-Lun, Chen, Huan-Wen, Lee, Che-I and Postula, Adam (2010). Constraint-based dogleg channel routing with via minimization. In: Hamid R. Arabnia, David de la Fuente, Elena B. Kozerenko and Jose A. Olivas, Proceedings of the 2010 International Conference on Artificial Intelligence (ICAI'10). 2010 International Conference on Artificial Intelligence (ICAI'10), Las Vegas, Nevada, United States, (666-672). 12-15 July 2010. 86   Cited 0 times in Scopus0
Tseng, I-Lun (2008). Estimation of Analog Layout Parasitics with Parameterized Polygons PhD Thesis, School of Information Technology and Electrical Engineering, The University of Queensland. 499 96
Tseng, I-Lun and Postula, Adam (2004). GBLD: A Formal Model for Layout Description and Generation. In: P. Boulet, Proccedings of the Forum on Specification and Design Languages. The Forum on Specification and Design Languages, Lille, France, (660-670). 14-17 September, 2004. 1654 531
Tseng, I-L. and Postula, A.J. (2008) Partitioning parameterized 45-degree polygons with constraint programming. Transactions on Design Automation of Electronic Systems, 13 3: 52:1-52:29. doi:10.1145/1367045.1367061 71   Cited 8 times in Scopus8 0